Altera Cyclone IV Device Handbook page 206

8–42
To ensure that DCLK and DATA[0] are not left floating at the end of the configuration,
the MAX II device must drive them either high or low, whichever is convenient on
your board. The DATA[0] pin is available as a user I/O pin after configuration. When
you choose the FPP scheme in the Quartus II software, the DATA[0] pin is tri-stated by
default in user mode and must be driven by the external host device. To change this
default option in the Quartus II software, select the Dual-Purpose Pins tab of the
Device and Pin Options dialog box.
The DCLK speed must be below the specified system frequency to ensure correct
configuration. No maximum DCLK period exists, which means you can pause
configuration by halting DCLK for an indefinite amount of time.
The external host device can also monitor the CONF_DONE and INIT_DONE pins to ensure
successful configuration. The CONF_DONE pin must be monitored by the external device
to detect errors and to determine when programming is complete. If all configuration
data is sent, but CONF_DONE or INIT_DONE has not gone high, the external device must
reconfigure the target device.
Figure 8–20
circuit is similar to the FPP configuration circuit for a single device, except the
Cyclone IV devices are cascaded for multi-device configuration.
Figure 8–20. Multi-Device FPP Configuration Using an External Host
External Host
(MAX II Device or
Microprocessor)
Notes to
(1) The pull-up resistor must be connected to a supply that provides an acceptable input signal for all devices in the
chain. V
(2) Connect the pull-up resistor to the V
(3) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(4) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect the MSEL pins,
refer to
(5) All I/O inputs must maintain a maximum AC voltage of 4.1 V. DATA[7..0] and DCLK must fit the maximum overshoot
outlined in
After the first device completes configuration in a multi-device configuration chain,
its nCEO pin drives low to activate the nCE pin of the second device, which prompts the
second device to begin configuration. The second device in the chain begins
configuration in one clock cycle; therefore, the transfer of data destinations is
transparent to the MAX II device. All other configuration pins (nCONFIG, nSTATUS,
Cyclone IV Device Handbook,
Volume 1
Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
shows how to configure multiple devices with a MAX II device. This
Memory
V (1) V
CCIO CCIO
ADDR DATA[7..0]
10 k 10 k
GND
Figure 8–20:
must be high enough to meet the V
CC
Table 8–4 on page 8–8 and Table 8–5 on page
Equation 8–1 on page 8–5.
(1)
Cyclone IV Device 1
(4)
MSEL[3..0]
CONF_DONE
nSTATUS
nCE nCEO
DATA[7..0] (5)
nCONFIG
DCLK (5)
Buffers (5)
specification of the I/O on the device and the external host.
IH
supply voltage of the I/O bank in which the nCE pin resides.
CCIO
8–9. Connect the MSEL pins directly to V
Configuration
V
(2)
CCIO
Cyclone IV Device 2
10 k
MSEL[3..0]
CONF_DONE
nSTATUS
nCE nCEO N.C. (3)
DATA[7..0] (5)
nCONFIG
DCLK (5)
or GND.
CCA
May 2013 Altera Corporation
(4)