Reset Sequence In Channel Reconfiguration Mode - Altera Cyclone IV Device Handbook

2–20
2. After the PLL is reset, wait for the pll_locked signal to go high (marker 4)
indicating that the PLL is locked to the input reference clock. After the assertion of
the pll_locked signal, deassert the tx_digitalreset signal (marker 5).
3. Wait at least five parallel clock cycles after the pll_locked signal is asserted to
deassert the rx_analogreset signal (marker 6).
4. When the rx_freqlocked signal goes high (marker 7), from that point onwards,
wait for at least t
(marker 8). At this point, the receiver is ready for data traffic.

Reset Sequence in Channel Reconfiguration Mode

Use the example reset sequence shown in
dynamic reconfiguration controller to change the PCS settings of the transceiver
channel. In this example, the dynamic reconfiguration is used to dynamically
reconfigure the transceiver channel configured in Basic ×1 mode with receiver CDR in
automatic lock mode.
Figure 2–12. Reset Sequence When Using the Dynamic Reconfiguration Controller to Change the
PCS Settings of the Transceiver Channel
Notes to
(1) For t
(2) The busy signal is asserted and deasserted only during initial power up when offset cancellation occurs. In
subsequent reset sequences, the busy signal is asserted and deasserted only if there is a read or write operation to
the ALTGX_RECONFIG megafunction.
Cyclone IV Device Handbook,
Volume 2
time, then deassert the rx_digitalreset signal
LTD_Auto
Reset and Control Signals
1
tx_digitalreset
1
rx_analogreset
1
rx_digitalreset
New value
reconfig_mode_sel[2..0]
1
write_all
Output Status Signals
busy (2)
channel_reconfig_done
rx_freqlocked
Figure 2–12:
duration, refer to the Cyclone IV Device Datasheet
LTD_Auto
Chapter 2: Cyclone IV Reset Control and Power Down
Dynamic Reconfiguration Reset Sequences
Figure 2–12 when you are using the
5
6
Five parallel clock cycles
2
3
4
7
t
LTD_Auto
chapter.
8
(1)
September 2014 Altera Corporation