Altera Cyclone IV Device Handbook page 354

1–74
Figure 1–66
deterministic latency mode.
Figure 1–66. Transceiver Channel Datapath and Clocking when Configured in Deterministic Latency Mode
FPGA
Fabric
tx_clkout
rx_clkout
Note to Figure 1–66:
(1) High-speed recovered clock.
Cyclone IV Device Handbook,
Volume 2
shows the transceiver channel datapath and clocking when configured in
Tx Phase
Comp Byte Serializer
FIFO
wr_clk rd_clk wr_clk
Rx
Byte Byte
Phase
Order- De-
Comp
serializer
ing
FIFO
/2
Chapter 1: Cyclone IV Transceivers Architecture
Transmitter Channel PCS
8B/10B Encoder
rd_clk
/2
Receiver Channel PCS
Rate
8B/10B Deskew
Match
Decoder FIFO
FIFO
Transceiver Functional Modes
Transmitter Channel PMA
Serializer
Receiver Channel PMA
Word Deserial-
CDR
Aligner izer
(1)
low-speed recovered clock
February 2015 Altera Corporation
high-speed
clock
low-speed clock
CDR clock