Altera Cyclone IV Device Handbook page 315

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Clocking Architecture
When the byte serializer is enabled, the low-speed clock frequency is halved before
feeding into the read clock of TX phase compensation FIFO. The low-speed clock is
available in the FPGA fabric as tx_clkout port, which can be used in the FPGA fabric
to send transmitter data and control signals.
Figure 1–33. Transmitter Only Datapath Clocking in Non-Bonded Channel Configuration
FPGA
Fabric
tx_datain
tx_coreclk
tx_clkout
Figure 1–34
receiver PCS supports configuration without the rate match FIFO. The CDR unit in
the channel recovers the clock from the received serial data and generates the high-
speed recovered clock for the deserializer, and low-speed recovered clock for
forwarding to the receiver PCS. The low-speed recovered clock feeds to the following
blocks in the receiver PCS:
■ word aligner
8B/10B decoder
■
■ write clock of byte deserializer
■ byte ordering
■ write clock of RX phase compensation FIFO
When the byte deserializer is enabled, the low-speed recovered clock frequency is
halved before feeding into the write clock of the RX phase compensation FIFO. The
low-speed recovered clock is available in the FPGA fabric as rx_clkout port, which
can be used in the FPGA fabric to capture receiver data and status signals.
Figure 1–34. Receiver Only Datapath Clocking without Rate Match FIFO in Non-Bonded Channel Configuration
FPGA
Fabric
rx_dataout
rx_coreclk
rx_clkout
Note to Figure 1–34:
(1) High-speed recovered clock.
When the transceiver is configured for transmitter and receiver operation in
non-bonded channel configuration, the receiver PCS supports configuration with and
without the rate match FIFO. The difference is only at the receiver datapath clocking.
The transmitter datapath clocking is identical to transmitter only operation mode as
shown in
February 2015 Altera Corporation
Tx Phase
Comp Byte Serializer
FIFO
wr_clk rd_clk wr_clk
shows the datapath clocking in receiver only operation. In this mode, the
Rx
Byte
Byte
Phase
De-
Order-
Comp
ing serializer
FIFO
/2
Figure 1–33.
Transmitter Channel PCS
8B/10B Encoder
rd_clk
/2
Receiver Channel PCS
Rate
8B/10B Deskew
Match
Decoder FIFO
FIFO
1–35
Transmitter Channel PMA
Serializer
high-speed
clock
low-speed clock
Receiver Channel PMA
Word Deserial-
CDR
Aligner izer
CDR clock
(1)
low-speed recovered clock
Cyclone IV Device Handbook,
Volume 2