Cyclone Iv Device Family Architecture; Fpga Core Fabric - Altera Cyclone IV Device Handbook

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Cyclone IV Device Family Architecture

This section describes Cyclone IV device architecture and contains the following
topics:

"FPGA Core Fabric"

■
"I/O Features"
■
■ "Clock Management"
■ "External Memory Interfaces"
■ "Configuration"
■ "High-Speed Transceivers (Cyclone IV GX Devices Only)"
"Hard IP for PCI Express (Cyclone IV GX Devices Only)"
■
FPGA Core Fabric
Cyclone IV devices leverage the same core fabric as the very successful Cyclone series
devices. The fabric consists of LEs, made of 4-input look up tables (LUTs), memory
blocks, and multipliers.
Each Cyclone IV device M9K memory block provides 9 Kbits of embedded SRAM
memory. You can configure the M9K blocks as single port, simple dual port, or true
dual port RAM, as well as FIFO buffers or ROM. They can also be configured to
implement any of the data widths in
Table 1–7. M9K Block Data Widths for Cyclone IV Device Family
Single port or simple dual port
True dual port
The multiplier architecture in Cyclone IV devices is the same as in the existing
Cyclone series devices. The embedded multiplier blocks can implement an 18 × 18 or
two 9 × 9 multipliers in a single block. Altera offers a complete suite of DSP IP
including finite impulse response (FIR), fast Fourier transform (FFT), and numerically
controlled oscillator (NCO) functions for use with the multiplier blocks. The
Quartus
MATLAB design environments for a streamlined DSP design flow.
f
For more information, refer to the
Devices,
Devices
Cyclone IV Device Handbook,
Volume 1
Mode
®
II design software's DSP Builder tool integrates MathWorks Simulink and
Memory Blocks in Cyclone IV
chapters.
Chapter 1: Cyclone IV FPGA Device Family Overview
Table 1–7.
Data Width Configurations
×1, ×2, ×4, ×8/9, ×16/18, and ×32/36
×1, ×2, ×4, ×8/9, and ×16/18
Logic Elements and Logic Array Blocks in Cyclone IV
Devices, and Embedded Multipliers in Cyclone IV
Cyclone IV Device Family Architecture
March 2016 Altera Corporation