Altera Cyclone IV Device Handbook page 486

1–40
Table 1–46. Glossary (Part 4 of 5)
Letter Term
t
C
Channel-to-
channel-skew
(TCCS)
t
cin
t
CO
t
cout
t
DUTY
t
FALL
t
H
Timing Unit
Interval (TUI)
t
INJITTER
t
OUTJITTER_DEDCLK
t
OUTJITTER_IO
t
pllcin
t
pllcout
T
Transmitter
Output
Waveform
t
RISE
t
SU
U —
Cyclone IV Device Handbook,
Volume 3
High-speed receiver and transmitter input and output clock period.
High-speed I/O block: The timing difference between the fastest and slowest output edges,
including t variation and clock skew. The clock is included in the TCCS measurement.
CO
Delay from the clock pad to the I/O input register.
Delay from the clock pad to the I/O output.
Delay from the clock pad to the I/O output register.
High-speed I/O block: Duty cycle on high-speed transmitter output clock.
Signal high-to-low transition time (80–20%).
Input register hold time.
High-speed I/O block: The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = t
Period jitter on the PLL clock input.
Period jitter on the dedicated clock output driven by a PLL.
Period jitter on the general purpose I/O driven by a PLL.
Delay from the PLL inclk pad to the I/O input register.
Delay from the PLL inclk pad to the I/O output register.
Transmitter output waveforms for the LVDS, mini-LVDS, PPDS and RSDS Differential I/O
Standards:
Single-Ended Waveform
V os
Differential Waveform (Mathematical Function of Positive & Negative Channel)
V
OD
Signal low-to-high transition time (20–80%).
Input register setup time.
Chapter 1: Cyclone IV Device Datasheet
Definitions
V
OD
V
OD
—
December 2016 Altera Corporation
Glossary
/w).
C
Positive Channel (p) = V
OH
Negative Channel (n) = V
OL
Ground
0 V
p - n