Word Aligner - Altera Cyclone IV Device Handbook

Chapter 1: Cyclone IV Transceivers Architecture
Receiver Channel Datapath

Word Aligner

Figure 1–16
data from the deserializer and restores the word boundary based on a pre-defined
alignment pattern that must be received during link synchronization. The word
aligner supports three operational modes as listed in
Figure 1–16. Word Aligner Block Diagram
data from
deserializer
rx_enapatternalign
rx_bitslip
rx_invpolarity
rx_revbitorderwa
Table 1–3. Word Aligner Modes
Manual Alignment
Bit-Slip
Automatic Synchronization State
Machine
Manual Alignment Mode
In manual alignment mode, the rx_enapatternalign port controls the word aligner
with either an 8- or 10-bit data width setting.
The 8-bit word aligner is edge-sensitive to the rx_enapatternalign signal. A rising
edge on rx_enapatternalign signal after deassertion of the rx_digitalreset signal
triggers the word aligner to look for the word alignment pattern in the received data
stream. It updates the word boundary if it finds the word alignment pattern in a new
word boundary. Any word alignment pattern received thereafter in a different word
boundary causes the word aligner to re-align to the new word boundary only if there
is a rising edge in the rx_enapatternalign signal.
The 10-bit word aligner is level-sensitive to the rx_enapatternalign signal. The word
aligner looks for the programmed 7-bit or 10-bit word alignment pattern or its
complement in the received data stream, if the rx_enapatternalign signal is held
high. It updates the word boundary if it finds the word alignment pattern in a new
word boundary. If the rx_enapatternalign signal is deasserted, the word aligner
maintains the current word boundary even when it receives the word alignment
pattern in a new word boundary.
February 2015 Altera Corporation
shows the word aligner block diagram. The word aligner receives parallel
Word Aligner
Receiver
Polarity
Inversion
Synchronization
State Machine
Run Length
Modes
Bit-Slip
Circuitry
Receiver
Bit
Manual Reversal
Alignment
Violation
PMA-PCS Interface Widths
8-bit
10-bit
8-bit
10-bit
10-bit
Table 1–3.
parallel data to
next PCS block
rx_bitslipboundaryselectout
rx_rlv
rx_syncstatus
rx_patterndetect
Allowed Word Alignment
Pattern Lengths
16 bits
7 or 10 bits
16 bits
7 or 10 bits
7 or 10 bits
Cyclone IV Device Handbook,
1–17
Volume 2