Reset Requirement; Gige Mode - Altera Cyclone IV Device Handbook

1–58
The compliance pattern is a repeating sequence of the four code groups: /K28.5/;
/D21.5/; /K28.5/; /D10.2/.
where the tx_forcedispcompliance port must be asserted in the same parallel clock
cycle as /K28.5/D21.5/ of the compliance pattern on tx_datain[15..0] port.
Figure 1–53. Compliance Pattern Transmission Support in PCI Express (PIPE) Mode

Reset Requirement

Cyclone IV GX devices meets the PCIe reset time requirement from device power up
to the link active state with the configuration schemes listed in
Table 1–18. Electrical Idle Inference Conditions
Note to
(1) EP4CGX30 device in F484 package fulfills the PCIe reset time requirement using FPP configuration scheme with

GIGE Mode

GIGE mode provides the transceiver channel datapath configuration for GbE
(specifically the 1000 Base-X physical layer device (PHY) standard) protocol
implementation. The Cyclone IV GX transceiver provides the PMA and the following
PCS functions as defined in the IEEE 802.3 specification for 1000 Base-X PHY:
8B/10B encoding and decoding
■
synchronization
■
If you enabled the auto-negotiation state machine in the FPGA core with the rate
match FIFO, refer to
Cyclone IV Device Handbook,
Volume 2
Figure 1–53
tx_datain[15..0]
tx_ctrldetect[1..0]
tx_forcedispcompliance
Device Configuration Scheme
EP4CGX15 Passive serial (PS)
EP4CGX22
(1)
EP4CGX30
EP4CGX50 Fast passive parallel (FPP)
EP4CGX75
EP4CGX110
EP4CGX150
Table 1–18:
configuration time of 41 ms.
"Clock Frequency Compensation" on page
Chapter 1: Cyclone IV Transceivers Architecture
shows the compliance pattern transmission
/K28.5/D21.5/ /K28.5/D10.2/ /K28.5/D21.5/
B5BC 4ABC
01
PS
PS
FPP
FPP
FPP
Transceiver Functional Modes
/K28.5/D10.2/
B5BC 4ABC
Table 1–17.
Configuration Time (ms)
51
92
92
41
41
70
70
1–63.
February 2015 Altera Corporation