Altera Cyclone IV Device Handbook page 73

Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Clock Networks
Figure 5–1
Figure 5–1. Clock Control Block
Static Clock Select (3)
CLK[n + 3]
inclk1
CLK[n + 2]
inclk0
CLK[n + 1]
CLK[n] (6)
inclk1
inclk0
Not applicable to
Cyclone IV E devices
Notes to Figure 5–1:
(1) The clkswitch signal can either be set through the configuration file or dynamically set when using the manual PLL switchover feature. The
output of the multiplexer is the input clock (f
(2) The clkselect[1..0] signals are fed by internal logic and are used to dynamically select the clock source for the GCLK when the device is in
user mode.
(3) The static clock select signals are set in the configuration file. Therefore, dynamic control when the device is in user mode is not feasible.
(4) Two out of four PLL clock outputs are selected from adjacent PLLs to drive into the clock control block.
(5) You can use internal logic to enable or disable the GCLK in user mode.
(6) CLK[ ] is not available on the left side of Cyclone IV E devices.
n
Each PLL generates five clock outputs through the c[4..0] counters. Two of these
clocks can drive the GCLK through a clock control block, as shown in
f
For more information about how to use the clock control block in the Quartus II
software, refer to the
October 2012 Altera Corporation
shows the clock control block.
C0
C1
f
IN
C2
PLL
C3
C4
CLKSWITCH (1)
C0
C1
f
IN
C2
PLL
C3
C4
CLKSWITCH (1)
) for the PLL.
IN
ALTCLKCTRL Megafunction User
Clock Control Block
Internal Logic
DPCLK
CLKSELECT[1..0] (2)
(4)
Enable/
Disable
Static Clock
Select (3)
Internal Logic (5)
Figure 5–1.
Guide.
Cyclone IV Device Handbook,
5–11
Global
Clock
Volume 1