Bypassing A Pll Counter; Dynamic Phase Shifting - Altera Cyclone IV Device Handbook

Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
PLL Reconfiguration
Table 5–10. Loop Filter Control of High Frequency Capacitor

Bypassing a PLL Counter

Bypassing a PLL counter results in a divide (N, C0 to C4 counters) factor of one.
Table 5–11
Table 5–11. PLL Counter Settings
X
X
Note to
(1) Bypass bit.
To bypass any of the PLL counters, set the bypass bit to 1. The values on the other bits
are then ignored.

Dynamic Phase Shifting

The dynamic phase shifting feature allows the output phase of individual PLL
outputs to be dynamically adjusted relative to each other and the reference clock
without sending serial data through the scan chain of the corresponding PLL. This
feature simplifies the interface and allows you to quickly adjust t
changing output clock phase shift in real time. This is achieved by incrementing or
decrementing the VCO phase-tap selection to a given C counter or to the M counter.
The phase is shifted by 1/8 the VCO frequency at a time. The output clocks are active
during this phase reconfiguration process.
Table 5–12
Table 5–12. Dynamic Phase Shifting Control Signals (Part 1 of 2)
Signal Name
phasecounterselect[2..0]
phaseupdown
phasestep
October 2012 Altera Corporation
LFC[1]
0
0
1
lists the settings for bypassing the counters in PLLs of Cyclone IV devices.
PLL Scan Chain Bits [0..8] Settings
LSB
X X X X X
X X X X X
Table 5–11:
lists the control signals that are used for dynamic phase shifting.
Description
Counter Select. Three bits decoded to select
either the M or one of the C counters for
phase adjustment. One address map to
select all C counters. This signal is registered
in the PLL on the rising edge of scanclk.
Selects dynamic phase shift direction; 1= UP,
0 = DOWN. Signal is registered in the PLL on
the rising edge of scanclk.
Logic high enables dynamic phase shifting.
LFC[0]
0
1
1
MSB
(1)
X X 1 PLL counter bypassed
(1)
X X 0 PLL counter not bypassed
Source
Logic array or I/O
pins
Logic array or I/O
pins
Logic array or I/O
pins
5–39
Setting (Decimal)
0
1
3
Description
delays by
CO
Destination
PLL
reconfiguration
circuit
PLL
reconfiguration
circuit
PLL
reconfiguration
circuit
Cyclone IV Device Handbook,
Volume 1