Altera Cyclone IV Device Handbook page 318

1–38
Figure 1–36
low-speed clock distributions for transceivers in F324 and smaller packages, and in
F484 and larger packages in bonded (×2 and ×4) channel configuration.
Figure 1–36. Clock Distribution in Bonded (×2 and ×4) Channel Configuration for Transceivers in
F324 and Smaller Packages.
Notes to
(1) Transceiver channels 2 and 3 are not available for devices in F169 and smaller packages.
(2) High-speed clock.
(3) Low-speed clock.
(4) Bonded common low-speed clock path.
Cyclone IV Device Handbook,
Volume 2
and Figure 1–37 show the independent high-speed clock and bonded
2 Bonded Channel Configuration
MPLL_2
TX PMA
Ch3
(1)
TX PMA
Ch2
Transceiver (1)
Block
TX PMA
Ch1
GXBL0
TX PMA
Ch0 (4)
MPLL_1
Figure 1–36:
Chapter 1: Cyclone IV Transceivers Architecture
4 Bonded Channel Configuration
(2)
MPLL_2
(3)
Ch3
(1)
Ch2
Transceiver (1)
Block
Ch1
GXBL0
Ch0
MPLL_1
Transceiver Clocking Architecture
(2)
(3)
TX PMA
TX PMA
TX PMA
TX PMA
(4)
February 2015 Altera Corporation