Altera Cyclone IV Device Handbook page 433

Chapter 3: Cyclone IV Dynamic Reconfiguration
Dynamic Reconfiguration Modes
Table 3–7
Table 3–7. ALTGX Megafunction Port List for PLL Reconfiguration Mode
(1)
Port Name
pll_areset [n..0]
pll_scandata
[n..0]
pll_scanclk
[n..0]
pll_scanclkena
[n..0]
pll_configupdate
[n..0]
pll_reconfig_done[n..0]
pll_scandataout
[n..0]
Note to Table 3–7:
(1) <n> = (number of transceiver PLLs configured in the ALTGX MegaWizard) - 1.
f
For more information about the ALTPLL_RECONFIG megafunction port list,
description and usage, refer to the
(ALTPL_RECONFIG) Megafunction User
November 2011 Altera Corporation
lists the ALTGX megafunction ports for PLL Reconfiguration mode.
Input/
Description
Output
Resets the transceiver PLL. The
pll_areset are asserted in two
conditions:
Used to reset the transceiver PLL
■
during the reset sequence. During
reset sequence, this signal is user
Input controlled.
After the transceiver PLL is
■
reconfigured, this signal is
asserted high by the
ALTPLL_RECONFIG controller. At
this time, this signal is not user
controlled.
Receives the scan data input from
Input the ALTPLL_RECONFIG
megafunction.
Drives the scanclk port on the
Input
reconfigurable transceiver PLL.
Acts as a clock enable for the
Input scanclk port on the reconfigurable
transceiver PLL.
Drives the configupdate port on
Input
the reconfigurable transceiver PLL.
This signal is asserted to indicate the
Output
reconfiguration process is done.
This port scan out the current
Output
configuration of the transceiver PLL.
You must connect the pll_areset port of ALTGX to the
pll_areset port of the ALTPLL_RECONFIG
megafunction.
The ALTPLL_RECONFIG controller asserts the
pll_areset port at the next rising clock edge after the
pll_reconfig_done signal from the ALTGX
megafunction goes high. After the pll_reconfig_done
signal goes high, the transceiver PLL is reset. When the
PLL reconfiguration is completed, this reset is
performed automatically by the ALTPLL_RECONFIG
megafunction and is not user controlled.
The reconfigurable transceiver PLL received the scan
data input through this port for the dynamically
reconfigurable bits from the ALTPLL_RECONFIG
controller.
Connect the pll_scanclk port of the ALTGX
megafunction to the ALTPLL_RECONFIG scanclk port.
Connect the pll_scanclkena port of the ALTGX
megafunction to the ALTPLL_RECONFIG scanclk port.
This port is connected to the pll_configupdate port
from the ALTPLL_RECONFIG controller. After the final
data bit is sent out, the ALTPLL_RECONFIG controller
asserts this signal.
Connect the pll_reconfig_done port to the
pll_scandone port on the ALTPLL_RECONFIG
controller. The transceiver PLL scandone output signal
drives this port and determines when the PLL is
reconfigured.
Connect the pll_scandataout port to the
pll_scandataout port of the ALTPLL_RECONFIG
controller. This port reads the current configuration of
the transceiver PLL and send it to the
ALTPLL_RECONFIG megafunction.
Phase-Locked Loop Reconfiguration
Guide.
3–35
Comments
Cyclone IV Device Handbook,
Volume 2