Altera Cyclone IV Device Handbook page 133

Table 6–8 and
device family.
Table 6–8. Cyclone IV E I/O and Differential Channel Count
User
91 179 179 91 179 179
(3)
I/O
User I/O
8 8 8 8 8
Banks
(4), (
LVDS
8 23 23 8 23
6)
Emulated
(5), (
LVDS 13 43 43 13 43
6)
Notes to Table 6–8:
(1) User I/O pins are used as inputs or outputs; clock input pins are used as inputs only; clock output pins are used as output only.
(2) For differential pad placement guidelines, refer to
(3) The I/O pin count includes all GPIOs, dedicated clock pins, and dual-purpose configuration pins. Dedicated configuration pins are not included in the pin count.
(4) The true LVDS count includes all LVDS I/O pairs, differential clock input and clock output pins in row I/O banks 1, 2, 5, and 6.
(5) The emulated LVDS count includes all LVDS I/O pairs, differential clock input and clock output pins in column I/O banks 3, 4, 7, and 8.
(6) LVDS input and output buffers are sharing the same p and n pins. One LVDS I/O channel can only be either transmitter or receiver at a time.
Table 6–9 summarize the total number of supported row and column differential channels in the Cyclone IV
81 89 165 165 165 343
8 8 8 8 8 8 8
23 6 8 21 21 21 67
43 12 13 32 32 32 70
"Pad Placement" on page 6–23.
79 153 153 193 328 532 193 328 328 532 324 324 374 292 292 426 280 528
8 8 8 8 8 8 8
7 20 20 30 60 112 30
10 32 32 38 64 112 38
8 8 8 8 8 8 8
60 60 112 62 62 70 54
64 64 112 70 70 90 56
8 8 8 8
54 79 50 103
56 99 53 127