Transceiver Functional Modes - Altera Cyclone IV Device Handbook

Chapter 1: Cyclone IV Transceivers Architecture

Transceiver Functional Modes

The hard IP block supports 1, 2, or 4 initial lane configurations with a maximum
payload of 256 bytes at Gen1 frequency. The application interface is 64 bits with a data
width of 16 bits per channel running at up to 125 MHz. As a hard macro and a verified
block, it uses very few FPGA resources, while significantly reducing design risk and
the time required to achieve timing closure. It is compliant with the PCI Express Base
Specification 1.1. You do not have to pay a licensing fee to use this module.
Configuring the hard IP block requires using the PCI Express Compiler.
f
For more information about the hard IP block, refer to the
Guide.
Figure 1–43
hard IP block.
Figure 1–43. PCIe with Hard IP Block Lane Placement Requirements
Note to
(1) Applicable for PCIe ×1, ×2, and ×4 implementations with hard IP blocks only.
Transceiver Functional Modes
The Cyclone IV GX transceiver supports the functional modes as listed in
for protocol implementation.
Table 1–14. Transceiver Functional Modes for Protocol Implementation (Part 1 of 2)
Functional Mode Protocol
Proprietary, SATA, V-
Basic
by-One, Display Port
PCI Express PCIe Gen1 with PIPE
(PIPE) Interface
GIGE
Serial RapidIO
XAUI
February 2015 Altera Corporation
shows the lane placement requirements when implementing PCIe with
PCIe Lane 3
PCIe Lane 2
PCIe Lane 1
PCIe Lane 0
Figure 1–43:
Low latency PCS, transmitter in electrical idle, signal
detect at receiver, wider spread asynchronous SSC
PIPE ports, receiver detect, transmitter in electrical
idle, electrical idle inference, signal detect at receiver,
fast recovery, protocol-compliant word aligner and
rate match FIFO, synchronous SSC
Running disparity preservation, protocol-compliant
GbE word aligner, recovered clock port for applications
such as Synchronous Ethernet
SRIO Protocol-compliant word aligner
Deskew FIFO, protocol-compliant word aligner and
XAUI
rate match FIFO
PCI Express Compiler User
Transceiver
Block GXBL0
Channel 3
Channel 2
PCIe
hard IP
Channel 1
Channel 0
Key Feature
1–47
(1)
Table 1–14
Reference
"Basic Mode" on
page 1–48
"PCI Express (PIPE)
Mode" on page 1–52
"GIGE Mode" on
page 1–59
"Serial RapidIO Mode"
on page 1–64
"XAUI Mode" on
page 1–67
Cyclone IV Device Handbook,
Volume 2