Operation As Pwm Output Mode - NEC 78K0 User Manual

9.4.2

Operation as PWM output mode

In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output.
8-bit timer compare register 0n (CMP0n) controls the cycle of timer output (TOHn). Rewriting the CMP0n register
during timer operation is prohibited.
8-bit timer compare register 1n (CMP1n) controls the duty of timer output (TOHn). Rewriting the CMP1n register
during timer operation is possible.
The operation in PWM output mode is as follows.
TOHn output becomes active and 8-bit timer counter Hn is cleared to 0 when 8-bit timer counter Hn and the
CMP0n register match after the timer count is started. TOHn output becomes inactive when 8-bit timer counter Hn
and the CMP1n register match.
(1) Usage
In PWM output mode, a pulse for which an arbitrary duty and arbitrary cycle can be set is output.
<1> Set each register.
(i) Setting timer H mode register n (TMHMDn)
TMHEn CKSn2
TMHMDn
0 0/1
(ii) Setting CMP0n register
• Compare value (N): Cycle setting
(iii) Setting CMP1n register
• Compare value (M): Duty setting
Remarks 1. n = 0, 1
2. 00H ≤ CMP1n (M) < CMP0n (N) ≤ FFH
<2> The count operation starts when TMHEn = 1.
<3> The CMP0n register is the compare register that is to be compared first after counter operation is enabled.
When the values of 8-bit timer counter Hn and the CMP0n register match, 8-bit timer counter Hn is cleared,
an interrupt request signal (INTTMHn) is generated, and TOHn output becomes active. At the same time,
the compare register to be compared with 8-bit timer counter Hn is changed from the CMP0n register to the
CMP1n register.
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CHAPTER 9 8-BIT TIMERS H0 AND H1
Figure 9-11. Register Setting in PWM Output Mode
CKSn1 CKSn0 TMMDn1
0/1 0/1 1
User's Manual U15947EJ2V0UD
TMMDn0 TOLEVn TOENn
0 0/1 1
*
Timer output enabled
Timer output level inversion setting
PWM output mode selection
Count clock (f ) selection
CNT
Count operation stopped