Dma Trigger Factor Registers 0 To 3 (Dtfr0 To Dtfr3) - NEC V850E/MS1 UPD703100 User Manual

6.3.6 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3)

These 8-bit registers are used to control the DMA transfer start trigger through interrupt requests from peripheral
I/O.
The interrupt requests that are set with these registers start DMA transfer.
These registers can be read/written in 8- or 1-bit units.
7 6
0 0
DTFR0
0 0
DTFR1
0 0
DTFR2
0 0
DTFR3
Bit Position Bit Name
5 to 0 IFCn5 to
IFCn0
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
5 4 3
IFC05 IFC04 IFC03
IFC15 IFC14 IFC13
IFC25 IFC24 IFC23
IFC35 IFC34 IFC33
Interrupt Factor Code
This code indicates the source of the DMA transfer trigger.
IFCn5 IFCn4 IFCn3
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 1
0 0 1
0 0 1
0 0 1
0 0 1
0 0 1
0 0 1
0 0 1
0 1 0
0 1 0
0 1 0
User's Manual U12688EJ4V0UM00
2 1 0
IFC02 IFC01 IFC00
IFC12 IFC11 IFC10
IFC22 IFC21 IFC20
IFC32 IFC31 IFC30
Function
IFCn2 IFCn1 IFCn0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
0 0 1
0 1 0
Address After reset
FFFFF5E0H 00H
FFFFF5E2H 00H
FFFFF5E4H 00H
FFFFF5E6H 00H
Interrupt Source
DMA request from
internal peripheral I/O
disabled.
INTCM40
INTCM41
INTCSI0
INTSR0
INTST0
INTCSI1
INTSR1
INTST1
INTCSI2
INTCSI3
INTP100/INTCC100
INTP101/INTCC101
INTP102/INTCC102
INTP103/INTCC103
INTP110/INTCC110
INTP111/INTCC111
INTP112/INTCC112
INTP113/INTCC113
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