Fig 6. External System Clock Configuration - NXP Semiconductors PN7150 Hardware Design Manual

NXP Semiconductors
Warning: XTAL1 pin is referenced to VDD(PAD) supply. Therefore VDD(PAD) must
always be supplied to the PN7150 when a valid input clock signal is required (i.e. to
generate an RF field)
The dedicated clock request pin (CLK_REQ) can be optionally connected to a clock
buffer. CLK_REQ pin is driven high when the NFCC needs an input clock. Otherwise it is
driven low.
Fig 6.
AN11756
Application note
COMPANY PUBLIC
External system clock configuration
All information provided in this document is subject to legal disclaimers.
Rev. 1.2 — 15 January 2018
347612
AN11756
PN7150 Hardware Design Guide
© NXP B.V. 2018. All rights reserved.
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