NXP Semiconductors PT2001 Programming Manual And Instruction Set

1

Introduction

2

Microcore programming description

2.1 CRAM addressing mode

2.2 Arithmetic logic unit

PT2001SWUG
PT2001 programming guide and instruction set
Rev. 3.0 — 29 April 2019
This programming guide relates to the PT2001 Programmable Solenoid Controller. Refer
to the individual device data sheet for feature information. The PT2001 programming
guide describes the microcore programming model, instruction set, data types used,
and basic memory organization. Also included in the guide is an example of microcode
used in the FRDMPT2001EVM using most of the instructions described herein. The
programming of the microcores has to be done using the PT2001 IDE, which is available
at https://www.nxp.com.
All the jump instructions have two possible outcomes: if a specific condition (if any) is
true, then the code flow continues at a destination specified by a parameter, otherwise
it continues to the next code line. In the same way, when a wait entry is configured, a
parameter specifies the destination.
The instruction set of PT2001 allows only two addressing modes to express the
destination parameter for the CRAM:
• Relative address (relative): The relative address parameter is represented by 5 bits.
The physical address of the destination is obtained by adding the relative address to
the physical address of the instruction that uses the parameter (that is the value of
the uprogram counter when the instruction is executed). The relative address must be
considered as two's complement represented and must be extended on 10 bit before
the addition. By using relative addresses it is possible to range from "current_address –
16" to "current_address + 15".
• Indirect address (far): It is possible to jump to the CRAM address contained into
one of two jump_registers (jr1 or jr2). These registers can be loaded with a dedicated
instruction and simply referred to in the wait or jump instructions. Refer to
in Section 3.2 "Instruction
The microcore contains a simple Arithmetic Logic Unit (ALU). The ALU has an 8-word
internal register file connected to the internal bus. The ALU can perform the following
operations:
• Addition and subtraction. These operations are completed in a single ck clock cycle.
• Multiplication. This operation is completed in up to 32 ck clock cycles. The result is
available as a 32-bit number, and is always in the registers GPR6 (MSBs) and GPR7
(LSBs).
set".
User guide
ldjr1 and ldjr2