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Enhanced Queued Analog-to-Digital Converter (EQADC)
25.7.6
ADC Result Calibration
The ADC result calibration process consists of two steps: determining the gain and offset calibration
constants, and calibrating the raw results generated by the on-chip ADCs by solving the following equation
discussed in
Section 25.6.6.7, ADC Calibration
The calibration constants GCC and OCC can be calculated from equation
pairs of expected (CAL_RES) and measured (RAW_RES) result values are available for two different
input voltages. Most likely calibration points to be used are 25% VREF
apart but not too close to the end points of the full input voltage range. This allows for calculations of more
representative calibration constants. The EQADC provides these voltages via channel numbers 43 and 44.
The raw, uncalibrated results for these input voltages are obtained by converting these channels with
conversion commands that have the CAL bit negated.
The transfer equations for when sampling these reference voltages are:
CAL_RES
= GCC * RAW_RES
75%VREF
CAL_RES
= GCC * RAW_RES
25%VREF
Thus;
GCC = (CAL_RES
75%VREF
OCC = CAL_RES
or
OCC = CAL_RES
After being calculated, the GCC and OCC values must be written to ADC registers:
ADC0/1 Gain Calibration Constant Registers (ADC0_GCCR and
ADC0/1 Offset Calibration Constant Registers (ADC0_OCCR and
configuration commands.
The EQADC will automatically calibrate the results, according to equation
conversion command that has its CAL bit asserted using the GCC and OCC values stored in the ADC
calibration registers.
For accurate calibration, the 25% VREF channel must be converted using
the Long Sample Time (LST) setting for either 64 or 128 ADC sample
cycles in the ADC Conversion Command Message (LST = 0b10 or 0b11).
1.
VREF=VRH-VRL
1164
Feature.
CAL_RES = GCC * RAW_RES + OCC+2;
+ OCC+2;
75%VREF
+ OCC+2;
25%VREF
– CAL_RES
) / (RAW_RES
25%VREF
– GCC*RAW_RES
75%VREF
– GCC*RAW_RES
25%VREF
NOTE
MPC5644A Microcontroller Reference Manual, Rev. 6
Equation 25-1
1
and 75% VREF since they are far
– RAW_RES
75%VREF
25%VREF
– 2;
75%VREF
– 2;
25%VREF
Section 25.5.3.4,
ADC1_GCCR), and
ADC1_OCCR), using write
Equation
25-1, of every
Freescale Semiconductor
Eqn. 25-1
provided that two
);
Eqn. 25-2
Eqn. 25-3
Eqn. 25-4
Section 25.5.3.5,
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