Detailed Signal Descriptions - NXP Semiconductors MPC5644A Reference Manual

Name
AN39
MA0
MA1
MA2
FCK
SDS
SDI
SDO
VDDA
VSSA
VRH
VRL
REFBYPC
ETRIG0
ETRIG1
ETRIG2
ETRIG3
ETRIG4
ETRIG5
25.4.2

Detailed signal descriptions

25.4.2.1 AN0/DAN0+ — Single-ended analog input/Differential analog input
positive terminal
AN0 is a single-ended analog input to the two on-chip ADCs. DAN0+ is the positive terminal of the
differential analog input DAN0 (DAN0+ - DAN0-).
25.4.2.2 AN1/DAN0— — Single-ended analog input/Differential analog input
negative terminal
AN1 is a single-ended analog input to the two on-chip ADCs. DAN0- is the negative terminal of the
differential analog input DAN0 (DAN0+ - DAN0-).
25.4.2.3 AN2/DAN1+ — Single-ended analog input/Differential analog input
positive terminal
AN2 is a single-ended analog input to the two on-chip ADCs. DAN1+ is the positive terminal of the
differential analog input DAN1 (DAN1+ - DAN1-).
Freescale Semiconductor
Table 25-1. External Signals (continued)
Port
Input Single-ended analog input
Output External multiplexer control signal
Output External multiplexer control signal
Output External multiplexer control signal
Output EQADC SSI free running clock
Output EQADC SSI serial data select
Input EQADC SSI serial data in
Output EQADC SSI serial data out
Input Analog Positive Power Supply
Input Analog Negative Power Supply
Input Voltage Reference High
Input Voltage Reference Low
Input External Bypass capacitor Pin
Input External trigger for CFIFO0
Input External trigger for CFIFO1
Input External trigger for CFIFO2
Input External trigger for CFIFO3
Input External trigger for CFIFO4
Input External trigger for CFIFO5
MPC5644A Microcontroller Reference Manual, Rev. 6
Enhanced Queued Analog-to-Digital Converter (EQADC)
Function Reset State Type
— Analog
0 Digital
0 Digital
0 Digital
0 Digital
1 Digital
Digital
0 Digital
— Power
— Power
— Power
— Power
— Power
— Digital
— Digital
— Digital
— Digital
— Digital
— Digital
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