A/D Trigger Control Register (Adtrgc) - Fujitsu MB91260B Series Hardware Manual

CHAPTER 11 MULTIFUNCTIONAL TIMER
11.4.4

A/D Trigger Control Register (ADTRGC)

This register controls the A/D trigger signal output when a free-run timer compare
match or a zero detection occurs.
■ A/D Trigger Control Register (ADTRGC)
AD trigger control register
Bit7 Bit6
-
-
R/W: Readable/Writable
: Initial value
- : Unused bit
Table 11.4-3 A/D Trigger Control Register (ADTRGC)
Bit Name
bit7
bit6
Unused bit
bit5
bit4
SEL2:
bit3
A/D2 trigger source select bit
SEL1:
bit2
A/D1 trigger source select bit
AD2E:
bit1
A/D2 trigger enable bit
AD1E:
bit0
A/D1 trigger enable bit
226
Bit5 Bit4 Bit3
- - - SEL2
- - -
R/W
• The read value is indeterminate.
• Writing to these bits have no effect on operation.
This bit is the select bit if A/D2 trigger is outputted when a zero detection of the free-
run timer or a compare match occurs.
This bit is the select bit if A/D1 trigger is outputted when a zero detection of the free-
run timer or a compare match occurs.
• When this bit is set to "0", the A/D2 trigger signal is not outputted.
• When this bit is set to "1", the A/D2 trigger signal can be outputted.
• When this bit is set to "0", the A/D1 trigger signal is not outputted.
• When this bit is set to "1", the A/D1 trigger signal can be outputted.
Bit2 Bit1 Bit0
SEL1 AD2E AD1E
R/W R/W R/W
AD1E A/D1 trigger output enable bit
0 Disable
1 Enable
AD2E A/D2 trigger output enable bit
0 Disable
1 Enable
SEL1 A/D1 trigger source select bit
0 At zero detection
1 At compare match
SEL2 A/D2 trigger source select bit
0 At zero detection
1 At compare match
Function
ADTRGC
Address: 0000AB
H
Initial value: XXXX0000
B