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CHAPTER 13 UART
■ Block Diagram
From U-TIMER
External clock
SCK
SIN (receive data)
Receive status
decision circuit
SMR
register
306
Clock
Receive clock
selection
circuit
Receive control
Start bit detection
Receive bit
Receive parity
Receive shifter
DMA receive error
occurrence signal
(to DMAC)
MD1
MD0
SCR
register
CS0
SCKE
Send clock
circuit
circuit
counter
counter
Receiving
ends
SIDR
R-bus
PEN
P
SBL
CL
register
A/D
REC
RXE
TXE
Receive interrupt
(to CPU)
SCK (clock)
Send interrupt
(to CPU)
Send control
circuit
Send start circuit
Send bit counter
Send parity
counter
SOT (send data)
Send shifter
Sending
starts
SODR
PE
ORE
FRE
SSR
RDRF
TDRE
BDS
RIE
TIE
Control signal
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