Fujitsu MB91260B Series Hardware Manual page 280

Notes:
• When the timer count clock is the machine cycle (φ)
Even if a software clear (TCCSL: bit4 SCLR = 1) is performed, the zero-detection interrupt flag is
not set, and a zero-detection interrupt is not generated.
• When the timer count clock is the machine cycle (φ) division
When a software clear (TCCSL: bit4 SCLR = 1) is performed, and the zero-detection interrupt flag
is set and interrupts are enabled, then a zero-detection interrupt is generated.
Figure 11.6-8 Compare Clear Interrupt Masked in Up Count Mode
Count value
FFFF
H
BFFF
H
7FFF
H
3FFF
H
0000
H
Start timer operation
Reset
Zero-detection
interrupt
TCCSH : MSI2 to MSI0=000
Compare clear
TCCSH : MSI2 to MSI0=001
interrupt
TCCSH : MSI2 to MSI0=010
Note: Both zero detection interrupt and compare clear interrupt are cleared by the software. Note: Both zero detection interrupt and compare clear interrupt are cleared by the software.
Figure 11.6-9 Zero Detection Interrupt Masked in Up/Down Count Mode
Count value
FFFF
H
BFFF
H
7FFF
H
3FFF
H
0000
H
Start timer operation
Reset
Compare clear
interrupt
TCCSH : MSI2 to MSI0=000
Zero-detection
TCCSH : MSI2 to MSI0=001
interrupt
TCCSH : MSI2 to MSI0=010
Note: Both zero detection interrupt and compare clear interrupt are cleared by the software. Note: Both zero detection interrupt and compare clear interrupt are cleared by the software.
1st 2nd
Software clear
B
B
B
1st 2nd 3rd
1st 2nd
Software clear
B
B
B
CHAPTER 11 MULTIFUNCTIONAL TIMER
3rd 4th
4th 5th
3rd 4th 5th
Time
6th
Time
6th
265