Fujitsu MB91260B Series Hardware Manual page 500

Initial Area
Vector Table Initial Area................................................... 44
Initial Value
Initial Value of Each Hardware....................................... 180
Initialization
Wait Times after Setting Initialization .............................. 72
Input Capture
16-bit Input Capture Interrupt ......................................... 258
16-bit Input Capture Registers ........................................ 215
Cautions for Use of 16-bit Input Capture........................ 292
Input Timing of 16-bit Input Capture.............................. 278
Operation of 16-bit Input Capture ................................... 277
Input Capture Data Register
Input Capture Data Register (IPCPH: IPCPH0 to
IPCPH3,IPCPL: IPCPL0 to IPCPL3) ............. 236
Input Capture State Control Register
Input Capture State Control Register (ch.2,ch.3),Upper Byte
(ICSH23) ......................................................... 237
Input Capture State Control Register (ch.2,ch.3),Lower Byte
(ICSL23).......................................................... 239
Input/Output Circuit
Input/Output Circuit Types ............................................... 18
Instruction
Instruction Definitions..................................................... 354
Instruction Overview......................................................... 31
JMP Instruction (Branching Command) ......................... 366
MAC Instruction.............................................................. 363
Processing of RETI Instruction ......................................... 61
STR Instruction (Transition Instruction)......................... 364
Instruction Operation
Instruction Operation....................................................... 359
INT
Processing of INT Instruction ........................................... 59
INTE
Processing of INTE Instruction......................................... 59
Internal Architecture
Internal Architecture.......................................................... 28
Internal Clock
Internal Clock Operation ................................................. 158
Internal Peripheral Request
Internal Peripheral Request ............................................. 387
Interrupt
16-bit Free-Run Timer Interrupt...................................... 256
16-bit Input Capture Interrupt ......................................... 258
16-bit Output Compare Interrupt..................................... 257
DMAC Interrupt Control................................................. 396
DTTI Interrupts ............................................................... 290
EIT (Exception,Interrupt,and Trap)................................... 48
External Interrupt Request Level .................................... 135
External Interrupt Source Register (EIRR (EIRR0,EIRR1):
External Interrupt Request Register)............... 132
Interrupt Levels ................................................................. 49
Interrupt Number............................................................. 144
Interrupt of 8/10-bit A/D Converter ................................ 341
Interrupt Stack ................................................................... 52
Interrupt/NMI Level Masking ........................................... 50
NMI (Non Maskable Interrupt) ....................................... 124
Occurrence of Interrupts and Timing for Setting Flags
.........................................................................316
Operating Procedure for an External Interrupt ................134
Operation of an External Interrupt...................................134
Operation of User Interrupt/NMI ......................................58
Peripheral Interrupt Clear by DMA.................................394
Precautions when Returning from STOP State Using
External Interrupt.............................................137
Timer Interrupt ................................................................264
Waveform Generator Interrupts.......................................259
Interrupt Control Register
Interrupt Control Register (ICR:ICR00 to ICR47)
.........................................................................118
Interrupt Enable Register
Interrupt Enable Register (ENIR (ENIR0,ENIR1): ENable
Interrupt Request Register)..............................132
Interrupt Mask
Interrupt Mask Function ..................................................264
Interruption
Interruption ......................................................................180
Inverted Mode
Operation of 16-bit Output Compare
(Inverted Mode,MOD1x=0) ............................267
IPCPH
Input Capture Data Register (IPCPH: IPCPH0 to
IPCPH3,IPCPL: IPCPL0 to IPCPL3)..............236
IPCPL
Input Capture Data Register (IPCPH: IPCPH0 to
IPCPH3,IPCPL: IPCPL0 to IPCPL3)..............236
J
JMP Instruction
JMP Instruction (Branching Command)..........................366
L
Linker
Linker (flnk911) ..............................................................458
Low-power Consumption
Low-power Consumption Modes ......................................96
M
MAC Instruction
MAC Instruction..............................................................363
Main Function
Main Function..................................................................368
Major Functions
Major Functions...............................................................114
Masking
Interrupt/NMI Level Masking ...........................................50
Measurement
Pulse Width Measurement Function................................184
Measuring
Details for Pulse Width Measuring Operation ................195
Memory Map
Memory Map .............................................................. 26
INDEX
,
42
485