Table of Contents
Advertisement
15.4
Instruction Detail Explanation
This section explains the instruction detail for using on the multiplication and addition
calculator.
■ MAC Instruction
Operation: ACC
LY-DLY
DSP-LY
Explanation: Add the result of multiplying X data from X-RAM and Y data from Y-RAM to the
Word count : 1 word (16-bit width)
Cycle count : 1 system clock cycle (2 cycles if STLY = 1)
Operation code:
[bit14] CLAC (Clear A
• Setting this bit causes the instruction to act as a multiplication instruction.
0: ACC← ACC + X data × Y data [multiplication and addition instruction]
1: ACC ← 0 + X data × Y data [multiplication instruction]
[bit13] STLY (Store LY)
• The following processing is performed when this bit is "1". If "0", the operation only is performed.
• After performing the operation, save the contents of the LY-DLY register at the Y-Addr address in Y-
RAM.
• The execution time only increases to two cycles when this bit is set.
[bit12] LDLY (Load LY)
• The following processing is performed when this bit is "1". If "0", the operation only is performed.
• During the operation, the contents of the Y-Addr address in Y-RAM are stored in the DSP-LY register.
[bit11 to bit6] X-Addr (X-RAM Address)
Address bits for specifying the location of the X data in X-RAM.
← ACC + X data × Y data
← DSP-LY
← Y data (LDLY = 1)
← LY-DLY (STLY = 1)
Y-RAM
accumulator. Also transfer the contents of the DSP-LY register to the LY-DLY register at the
same time.
15
14
13
1
CLAC
STLY
)
CC
CHAPTER 15 MULTIPLICATION AND ADDITION CALCULATOR
12
11 . . . . . . . . . 6
LDLY
X-Addr
5 . . . . . . . . . . . 0
Y-Addr
363
Advertisement
Table of Contents
