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Notes:
Special example of operation modes and reload operation
• If you want to halt transfer after it completes and to restart after another input is detected, do not
use the reload function.
• When using burst, block, or step transfer modes, transfer halts after the reload is performed at the
end of the transfer operation, and no further transfer is performed until a new transfer request
input is detected.
■ Addressing Mode
Specify the transfer destination and transfer source addresses independently for each transfer channel.
The following procedure can be used to set the registers. Set up the registers in accordance with the transfer
sequence.
●
Address registers
In two-cycle transfer mode, set the transfer source address in the transfer source address setting register
(DMASA) and set the transfer destination address in the transfer destination address setting register
(DMADA).
Features of address register
These registers are 20-bit for ch0 to ch3 and 24-bit for ch4.
Function of address register
•
The registers are read at each time when an access is performed and outputted on the address bus.
•
At the same time, the address counter is used to calculate the address for the next access and the
result of this calculation is set in the address register.
•
The address calculation is selected by increment or decrement independently for each channel,
transfer destination and source. The increment or decrement width of address depends on the value
of address count size specification register. (DMACB:SASZ, DASZ)
•
When the reload function is not enabled for an address register, the result of the final address
calculation remains in the register after the transfer ends.
•
If the reload function is enabled, the initial value of the address is reloaded.
Notes:
• Transfer continues even if an overflow or underflow occurs for the full 20-bit or 24-bit address
calculation. When setting up each channel, take care to ensure that overflow or underflow does
not occur.
• Do not set the addresses of registers in the DMAC in the address registers.
CHAPTER 16 DMAC (DMA Controller)
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