Fujitsu MB91260B Series Hardware Manual page 279

CHAPTER 11 MULTIFUNCTIONAL TIMER
■ Timer Interrupt
The 16-bit free-run timer can generate the following two interrupts.
• Compare clear interrupt
• Zero detection interrupt
Compare-clear interrupts are generated when the timer value matches the value of the compare-clear
register (CPCLRH, CPCLRL).
Zero-detection interrupts are generated when the timer value reaches "0000
Notes:
• When the timer count clock is the machine cycle (φ)
Even if a software clear (TCCSL: bit4 SCLR = 1) is performed, the zero-detection interrupt flag is
not set, and a zero-detection interrupt is not generated.
• When the timer count clock is the machine cycle (φ) division
When a software clear (TCCSL: bit4 SCLR = 1) is performed, and the zero-detection interrupt flag
is set and interrupts are enabled, then a zero-detection interrupt is generated.
Count value
Compare clear interrupt
Zero-detection interrupt
Count value
Compare clear interrupt
Zero-detection interrupt
■ Interrupt Mask Function
It is possible to mask interrupt requests by setting the TCCSH register MSI 2 to MSI0: bit12 to bit10. MSI2
to MSI0 bits are a 3-bit reload down counter that reload when the count value reaches 000
value can be reloaded by writing directly to MSI2 to MSI0 bits. The mask count is the value set in MSI2 to
MSI0 bits. When MSI2 to MSI0 bits are 000
The interrupt cause depends on the count mode (TCCSL register MODE: bit5). In up count mode, it is only
possible to mask compare-clear interrupts, and zero-detection interrupts are generated each time "0" is
detected. In up/down count mode, it is only possible to mask zero-detection interrupts, and compare-clear
interrupts are generated each time a compare clear is detected.
264
Figure 11.6-6 Interrupt Generated in Up Count Mode
(TCCSL Register MODE: Bit5 = 0)
N-1
Figure 11.6-7 Interrupt Generated in Up/Down Count Mode
(TCCSL Register MODE: Bit5 = 1)
N-1
N
N
0
N-1
, interrupt causes are not masked.
B
".
H
1
0
. The counter
B