Fujitsu MB91260B Series Hardware Manual page 70

Table 3.8-3 Vector Table (3 / 3)
Interrupt source
PWC0 (Measurement complete)
PWC1 (Measurement complete)
PWC0 (Overflow)
PWC1 (Overflow)
ICU 0 (Capture)
ICU 1 (Capture)
ICU 2/3 (Capture)
OCU0/1 (Match)
OCU2/3 (Match)
OCU4/5 (Match)
Delayed interrupt source bit
System-reserved (Used by REALOS)
System-reserved (Used by REALOS)
System-reserved
System-reserved
System-reserved
System-reserved
System-reserved
System-reserved
System-reserved
System-reserved
System-reserved
System-reserved
System-reserved
System-reserved
System-reserved
System-reserved
Used by INT instruction
*: Even when the TBR value is changed, the reset vector and mode vector are always fixed at addresses "000FFFFC
"000FFFF8 ", respectively.
H
Interrupt No.
Interrupt level
Dec Hex
53 35 ICR37
54 36 ICR38
55 37 ICR39
56 38 ICR40
57 39 ICR41
58 3A ICR42
59 3B ICR43
60 3C ICR44
61 3D ICR45
62 3E ICR46
63 3F ICR47
64 40
65 41
66 42
67 43
68 44
69 45
70 46
71 47
72 48
73 49
74 4A
75 4B
76 4C
77 4D
78 4E
79 4F
80 50
to to
255 FF
CHAPTER 3 CPU AND CONTROL UNITS
Offset
328
H
324
H
320
H
31C
H
318
H
314
H
310
H
30C
H
308
H
304
H
300
H
2FC
–
H
2F8
–
H
2F4
–
H
2F0
–
H
2EC
–
H
2E8
–
H
2E4
–
H
2E0
–
H
2DC
–
H
2D8
–
H
2D4
–
H
2D0
–
H
2CC
–
H
2C8
–
H
2C4
–
H
2C0
–
H
2BC
H
– to
000
H
TBR default address
000FFF28
H
000FFF24
H
000FFF20
H
000FFF1C
H
000FFF18
H
000FFF14
H
000FFF10
H
000FFF0C
H
000FFF08
H
000FFF04
H
000FFF00
H
000FFEFC
H
000FFEF8
H
000FFEF4
H
000FFEF0
H
000FFEEC
H
000FFEE8
H
000FFEE4
H
000FFEE0
H
000FFEDC
H
000FFED8
H
000FFED4
H
000FFED0
H
000FFECC
H
000FFEC8
H
000FFEC4
H
000FFEC0
H
000FFEBC
H
to
000FFC00
H
" and
H
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