Fujitsu MB91260B Series Hardware Manual page 148

■ External Interrupt Request Level Setting Register (ELVR (ELVR0,ELVR1): External
LeVel Register)
ELVR0 Address: 00000042
ELVR1 Address: 000000BA
ELVR0 Address: 00000043
ELVR1 Address: 000000BB
ELVR is a register to select request detections. In ELVR, two bits each are assigned to INT0 to INT9,
which results in the settings shown in table below. When each bit of the EIRR is cleared while the level is
in the request input level, an appropriate bit is set again as long as the input is at active level.
Set "H" level or "L" level request when returning from the stop state.
Table 6.2-1 Assignment of ELVR
LB9 to LB0, LA9 to LA0
Detection level of NMI is always a falling edge level. Also, when using NMI to return from the stop state,
detection level is "L" level.
CHAPTER 6 EXTERNAL INTERRUPT AND NMI CONTROLLER
Bit No. →
15 14
LB7 LA7 LB6
H
– –
H
Bit No. →
7 6
LB3 LA3 LB2
H
– –
H
0 0 "L" level indicates the existence of a request
B
0 1 "H" level indicates the existence of a request
B
1 0 A rising edge indicates the existence of a request
B
1 1 A falling edge indicates the existence of a request
B
13 12 11 10
LA6 LB5 LA5
– – – –
5 4 3 2
LA2 LB1 LA1
LB9 LA9
– –
9 8 Initial value
00000000 [R/W]
LB4 LA4
B
- - - - - - - - [R/W]
– –
B
1 0 Initial value
00000000 [R/W]
LB0 LA0
B
- - - - 0 0 0 0 [R/W]
LB8 LA8
B
Operation
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