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CHAPTER 11 MULTIFUNCTIONAL TIMER
Table 11.4-4 Compare Control Register, Upper Byte (OCSH1, OCSH3, OCSH5) (1 / 2)
Bit Name
bit15 Unused bit
BTS1:
bit14
Buffer transition
selection bit
BTS0:
bit13
Buffer transition
selection bit
CMOD:
bit12
Output level
reverse mode bit
230
• The read value is indeterminate.
• Writing to this bit has no effect on operation.
• This bit is used to select the time when the data is transferred from the output compare buffer
registers (OCCPBH0, OCCPBH2, OCCPBH4, OCCPBL0, OCCPBL2, OCCPBL4) to the output
compare registers (OCCPH1, OCCPH3, OCCPH5, OCCPL1, OCCPL3, OCCPL5).
• Setting this bit to "0" starts the data transfer when the count value 0 of the 16-bit free-run
timer is detected.
• Setting this bit to "1" starts the data transfer when a compare clear match of the 16-bit free-
run timer occurs.
• This bit is used to select the time when the data is transferred from the output compare buffer
registers (OCCPBH0, OCCPBH2, OCCPBH4, OCCPBL0, OCCPBL2, OCCPBL4) to the output
compare registers (OCCPH1, OCCPH3, OCCPH5, OCCPL1, OCCPL3, OCCPL5).
• Setting this bit to "0" starts the data transfer when the count value 0 of the 16-bit free-run
timer is detected.
• Setting this bit to "1" starts the data transfer when a compare clear match of the 16-bit free-
run timer occurs.
• This bit is used to switch the pin output level reverse mode immediately when the match
occurs while the pin output is enabled (OTE1 = 1 or OTE0 = 1).
• When this bit is set to "0":
The compare mode control register (OCMOD): MOD1x = 0
- RT0, RT2, RT4: The level is reversed immediately when the compare registers 0, 2, 4
match the 16-bit free-run timer.
- RT1, RT3, RT5: The level is reversed immediately when the compare registers 1, 3, 5
match the 16-bit free-run timer.
The compare mode control register (OCMOD): MOD1x = 1
- Set to "1" when the match occurs in the up count mode.
- Reset to "0" when the match occurs in the down count mode.
• When this bit is set to "1":
The compare mode control register (OCMOD): MOD1x = 0
- RT0, RT2, RT4: The level is reversed immediately when the compare registers 0, 2, 4
match the 16-bit free-run timer.
- RT1, RT3, RT5: The level is reversed immediately when the compare registers (0 or 1)
(2 or 3) (4 or 5) match the 16-bit free-run timer.
When the value of the compare register 0, 2, 4 and 1, 3, 5 is the same, the operation is the
same operation as only one compare register is used.
The compare mode control register (OCMOD): MOD1x = 1
- Reset to "0" when the match occurs in the up count mode.
- Set to "1" when the match occurs in the down count mode.
Function
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