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CHAPTER 13 UART
●
Start of Communication
Write to the SODR register to start communication. If only reception is performed, dummy send data must
be written to the SODR register.
●
End of Communication
Check for the end of communication by making sure that the RDRF flag of the SSR register has changed to
"1". Use the ORE bit of the SSR register to check that communication has been performed correctly.
■ Occurrence of Interrupts and Timing for Setting Flags
The UART has five flags and two interrupt sources.
The five flags are PE, ORE, FRE, RDRF, and TDRE. PE means parity error, ORE means overrun error,
and FRE means framing error. These flags are set when an error occurs during reception and are cleared
when "0" is written to REC of the SCR register. RDRF is set when receive data is loaded into the SIDR
register and is cleared when data is read from the SIDR register. However, Mode 1 does not provide a
parity detection function and Mode 2 does not provide a parity detection function and a framing error
detection function. TDRE is set when the SODR register is empty and writing to it is enabled, and is
cleared when data is written to the SODR register.
There are two interrupt sources, one for receiving and the other for sending. During receiving, an interrupt
is requested by PE, ORE, FRE, or RDRF. During sending, an interrupt is requested by TDRE. The
following shows the timing for setting the interrupt flags in each of these modes.
●
Receive Operation in Mode 0
The PE, ORE, FRE, and RDRF flags are set when the last stop bit is detected after a receive transfer is
completed, and an interrupt request is generated to the CPU. The SIDR data is invalid while PE, ORE, and
FRE are active.
Figure 13.3-3 Timing for Setting ORE, FRE, and RDRF (Mode 0)
PE, ORE, FRE
Receive interrupt
316
D6
Data
RDRF
D7
Stop
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