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Serial Onboard Writing
Pins Used for Fujitsu Standard Serial Onboard Writing
......................................................................... 433
Serial Output Data Register
SIDR: SIDR0 to SIDR2 (Serial Input Data Register)
SODR: SODR0 to SODR2
(Serial Output Data Register) .......................... 310
Serial Programming Connection
Basic Configuration of the Serial Programming Connection
......................................................................... 432
Example of Serial Programming Connection.................. 434
Serial Status Register
SSR: SSR0 to SSR2 (Serial Status Register) .................. 310
Set/Reset Mode
Operation of 16-bit Output Compare
(Set/Reset Mode,MOD15 to MOD10=1)
......................................................................... 271
Setting
Notes on Setting Register ................................................ 371
SIDR
SIDR: SIDR0 to SIDR2 (Serial Input Data Register)
SODR: SODR0 to SODR2
(Serial Output Data Register) .......................... 310
SIGCR
DTTI Operation of Waveform Control Register 2
(SIGCR2) ........................................................ 290
Waveform Control Register 1 (SIGCR1)........................ 251
Waveform Control Register 2 (SIGCR2)........................ 253
Signal
Ready/Busy Signal (RDY/BUSY) .................................. 420
sim911
Debugger (sim911,eml911,mon911)............................... 459
Single Conversion
Operation of Single Conversion Mode............................ 342
Sleep Mode
DMA Transfer in Sleep Mode......................................... 396
Returning from Standby Mode (Stop or Sleep Mode)
......................................................................... 125
Slot
Branch Operation with Delay Slot .................................... 45
Branch Operation without Delay Slot ............................... 47
SMR
SMR (Serial Mode Register)........................................... 307
SODR
SIDR: SIDR0 to SIDR2 (Serial Input Data Register)
SODR: SODR0 to SODR2
(Serial Output Data Register) .......................... 310
Software Request
Software Request............................................................. 387
Source Clock
Selecting the Source Clock Signal .................................... 70
SSR
SSR: SSR0 to SSR2 (Serial Status Register) .................. 310
Stack
Interrupt Stack ................................................................... 52
Standby
Return from Standby ....................................................... 134
Standby Control Register
STCR: Standby Control Register ......................................78
Standby Mode
Returning from Standby Mode (Stop or Sleep Mode)
.........................................................................125
Start-stop Synchronization
Asynchronous (Start-stop Synchronization) Mode
.........................................................................314
State Transitions
Device States and State Transitions...................................93
STCR
STCR: Standby Control Register ......................................78
Step
Processing of Step Trace Trap...........................................59
Step/block Transfer
Step/block Transfer Two-cycle Transfer .........................389
STOP
Precautions when Returning from STOP State Using
External Interrupt.............................................137
Return Operation from STOP State.................................138
Stop
Returning from Standby Mode (Stop or Sleep Mode)
.........................................................................125
Stop Mode
Wait Times after Returning from Stop Mode....................72
Stopping
Operation End/Stopping ..................................................395
Stopping due to Error ......................................................395
STR Instruction
STR Instruction (Transition Instruction) .........................364
Synchronous Mode
CLK Synchronous Mode .................................................315
System Configuration
System Configuration of AF200 Flash Microcontroller
Programmer (Yokogawa Digital Computer
Corporation).....................................................435
T
Table Base Register
TBR (Table Base Register)................................................53
TBCR
TBCR: Timebase Counter Control Register......................81
TBR
TBR (Table Base Register)................................................53
TCCSH
Timer State Control Register,Upper Byte (TCCSH)
.........................................................................221
TCCSL
Timer State Control Register,Lower Byte (TCCSL).......224
TCDTH
Timer Data Register (TCDTH,TCDTL)..........................220
TCDTL
Timer Data Register (TCDTH,TCDTL)..........................220
Temporary Sector Protect Cancel
Temporary Sector Protect Cancel....................................429
INDEX
489
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