Fujitsu MB91260B Series Hardware Manual page 414

32-bit microcontroller
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■ Burst Transfer
Burst transfer
- Starting is possible by all starting factors (option)
- Accessing is possible to all areas
- Setting of block number is possible.
- Generating interrupt clear at designated transfer number end and generating DMA interrupt.
Figure 16.7-2 Flowchart of Burst Transfer
DMA stop
DENB=>0
Wait start request
Reload enable
Load address, transfer
count, and block number
Address operation for
transfer source address access
Address operation for
transfer destination address access
Block number - 1
Transfer count - 1
Write back address, transfer
count, and block number
Clear interrupt
DMA transfer end
CHAPTER 16 DMAC (DMA Controller)
DENB=1
Initial
BLK=0
DTC=0
At only select peripheral interrupt start source
Generating interruption clear
Generating DMA interrupt
399

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