Fujitsu MB91260B Series Hardware Manual page 389

CHAPTER 16 DMAC (DMA Controller)
[bit23 to bit20] (Reserved): Unused bit
Reading value is fixed to "0000
[bit19 to bit16] BLK3 to BLK0 (BLocK size): Block size setting
Specifies the size for block transfer on the corresponding channel. The value set in these bits specifies the
number of words to transfer for each transfer operation (or, more exactly, the number of times transfer of
the specified word size is repeated). Always set "01
BLK
XXXX
• Initialized to "0000
• The read / write is possible.
• If all-zeros are specified, the block size is set to 16 words.
• Reading always returns the block size (reload value).
[bit15 to bit00] DTC15 to DTC0 (Dma Terminal Count register) *: Transfer count register
This register stores the number of transfers performed. Each register consists of 16 bits.
Each register has its own reload register. On channels that allow the transfer count register to be reloaded,
the initial value is automatically returned to the register when the transfer completes.
DTC
XXXX
When DMA transfer starts, the data in this register is stored to the counter buffer in the dedicated DMA
transfer counter and the value decremented by one after each transfer. When DMA transfer completes, the
value of the counter buffer is written back to this register and the DMA operation ends. Accordingly, you
cannot use this register to read the specified number of transfers during a DMA operation.
• Initialized to "00000000_00000000
• The read / write is possible. Always use halfword or word access to access the DTC register.
• Reading the register returns the counter value. You cannot read the reload value.
374
". Writing has no effect.
B
Specifying of block size for corresponding channel
" when resetting.
B
Specifying the number of transfers for corresponding channel
" when resetting.
B
" (size 1) when not performing block transfer.
H
Function
Function