Fujitsu MB91260B Series Hardware Manual page 14

Main changes in this edition
Page
■ Sample Program is added.
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● Note on Operation in PLL Clock Mode is changed.
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Table 3.8-3 Vector Table (1 / 3) is changed.
(Instruction break exception → System-reserved)
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(Operand break trap → System-reserved)
● Watchdog reset is changed.
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(WPR (watchdog reset defer register) → CTBR (timebase counter clear register))
■ Selecting the Source Clock Signal is changed.
(φ is the base clock that is generated from the source clock divided by two or by using the PLL oscillation.
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Therefore, the system base clock is a clock generated in the above-mentioned internal base clock generation.
is added.)
Figure 3.11-1 Block Diagram of the Clock Generation Control Unit is changed.
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(The WPR register part of [Watchdog controller] is deleted.)
The table in [bit9, bit8] WT1,WT0 (Watchdog interval Time select) is changed.
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(WPR → CTBR)
■ STCR: Standby Control Register is changed.
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■ CTBR: Timebase Counter Clear Register is changed.
(Note, however, that the FF is cleared automatically when the CPU is not operating such as in the stop or
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sleep mode or during DMA transfer. If such a condition develops, therefore, a watchdog reset is deferred
automatically. For details, see the section "3.11.7 Peripheral Circuits in the Clock Control Unit". is added.)
■ WPR: Watchdog Reset Defer Register in 3.11.6 Registers in the Clock Generation Control Unit is deleted.
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[Deferring the generation of a watchdog reset] in ● Watchdog timer is changed.
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(WPR (watchdog reset defer register) → CTBR (timebase counter clear register))
● Sleep mode is changed.
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● Stop mode is changed.
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Table 5.3-1 Interrupt Sources, Interrupt Numbers, and Interrupt Levels (1 / 3) is changed.
(Instruction break exception → System-reserved)
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(Operand break trap → System-reserved)
■ Precautions when Returning from STOP State Using External Interrupt is added.
137
■ Return Operation from STOP State is added.
138
■ Features of UART is changed.
304
(• The DMAC interrupt source is cleared by the writing operation to the DRCL register. is deleted.)
■ Register List is changed.
305
(DRCL part is deleted.)
■ DRCL is deleted.
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■ Precautions on Usage is changed.
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(Write to the DRCL register before starting DMA transfer by an interrupt for the first time. is deleted.)
Changes (For details, refer to main body.)
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