Fujitsu MB91260B Series Hardware Manual page 52

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ILM (Interrupt Level Mask) register
20
ILM4
The ILM register holds the interrupt level mask value to be used for level masking.
An interrupt request to the CPU is accepted only when its interrupt level is higher than the level held in the
ILM register.
The level value ranges from 0 (00000
The level value which can be set from the program is limited.
When the original value is 16 to 31:
The new value which can be set is 16 to 31. After an instruction which sets a value of 0 to 15 is
executed, a value of (the specified value + 16) is transferred.
When the original value is 0 to 15:
Any value from 0 to 31 can be set.
This register is initialized to 15 (01111
[Notes on the PS register]
Since some instructions manipulate the PS register earlier, the following exceptions may cause the interrupt
service routine to break or the PS flag to update its display setting when the debugger is being used.
As the device is designed to carry out reprocessing correctly upon returning from such an EIT event in
either case, it performs operations before and after the EIT as specified.
1. The following operations may be performed when the instruction immediately followed by a DIV0U/
DIV0S instruction is (a) accepted by a user interrupt or NMI, (b) single-stepped, or (c) breaks in
response to a data event or emulator menu:
(1) The D0 and D1 flags are updated earlier.
(2) The EIT service routine (user interrupt/NMI or emulator) is executed.
(3) Upon returning from the EIT, the DIV0U/DIV0S instruction is executed and the D0 and D1 flags
are updated to the same values as those in (1) above.
2. The following operations are performed when the ORCCR/STILM/MOV Ri and PS instructions are
executed to enable interrupts when a user interrupt or NMI trigger event has occurred.
(1) The PS register is updated earlier.
(2) The EIT service routine (user interrupt/NMI) is executed.
(3) Upon returning from the EIT, the above instructions are executed and the PS register is updated to
the same value as that in (1) above.
19 18 17
ILM3 ILM2 ILM1 ILM0
) for the highest level to 31 (11111
B
) at a reset.
B
CHAPTER 3 CPU AND CONTROL UNITS
16 [Initial value]
01111
B
B
) for the lowest.
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