Register Of Ppg - Fujitsu MB91260B Series Hardware Manual

CHAPTER 9 PPG (Programmable Pulse Generator)
9.3

Register of PPG

This section describes the PPG registers.
■ PPGCn Register (PPGn Operation Mode Control Register)
Figure 9.3-1 PPGCn Register (PPGn Operation Mode Control Register)
PPGC0 to PPGC15 operation mode control register (PPGCn)
Address:
ch 0 :000108
H
ch 1 :000109
H
ch 2 :00010A
H
ch 3 :00010B
H
ch 4 :000114
H
ch 5 :000115
H
ch 6 :000116
H
ch 7 :000117
H
ch 8 :000120
H
ch 9 :000121
H
ch10 :000122
H
ch11 :000123
H
ch12 :00012C
ch13 :00012D
ch14 :00012E
H
ch15 :00012F
H
[bit7] PIEn (Ppg Interrupt Enable): PPG interrupt enable bit
This bit controls a PPG interrupt enable as described below.
0
1
• If this bit is set to "1", an interrupt request is generated when the PUFn is set to "1".
• If this bit is set to "0", no interrupt request is generated.
• Initialized to "0" by reset.
• The read / write is possible.
[bit6] PUFn (Ppg Underflow Flag): PPG counter underflow bit
This bit controls PPG counter underflow bit as described below.
0
1
• In the 8-bit PPG 2ch mode and the 8-bit prescaler + 8-bit PPG mode, this bit is set to "1" when the count
value of ch0 underflows from "00
• In the 16-bit PPG 1ch mode, this bit is set to "1" when the count value of ch1/ch0 underflows from
"0000
• Writing "0" clears the bit to "0".
172
n=0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
Bit7
PIEn
Read/Write →
R/W
Initial value →
(0)
H
H
Disables the interrupt.
Enables the interrupt.
PPG counter underflow has not been detected.
PPG counter underflow has been detected.
" to "FFFF ".
H H
n = 0 to 15
Bit6 Bit5 Bit4
PUFn INTMn PCS1
R/W R/W R/W
(0) (0) (0)
" to "FF ".
H H
Bit3 Bit2 Bit1
PCS0 MD1 MD0
R/W R/W R/W
(0) (0) (0)
Bit0
-
-
(X)