Fujitsu MB91260B Series Hardware Manual page 248

Table 11.4-5 Compare Control Register, Lower Byte (OCSL0, OCSL2, OCSL4)
Bit Name
IOP1:
bit7 Compare match
interrupt flag bit
IOP0:
bit6 Compare match
interrupt flag bit
IOE1:
bit5 Compare match
interrupt enable bit
IOE0:
bit4 Compare match
interrupt enable bit
BUF1:
bit3 Compare buffer
disable bit
BUF0:
bit2 Compare buffer
disable bit
CST1:
bit1 Compare operation
enable bit
CST0:
bit0 Compare operation
enable bit
• This bit is an interrupt flag which indicates that the compare register 1, 3, 5 matches the
value of the 16-bit free-run timer.
• This bit is set to "1" when the value of the compare register matches the value of the 16-bit
free-run timer.
• When this bit is set while the compare match interrupt enable bit (IOE1: bit5) is enabled, the
output compare interrupt occurs.
• When this bit is set to "0": Clears the bit.
• Setting this bit to "1" has no effect on this bit.
• When this bit is read to a read modify write instruction, "1" is always read.
• This bit is an interrupt flag which indicates that the compare register 0, 2, 4 matches the
value of the 16-bit free-run timer.
• This bit is set to "1" when the value of the compare register matches the value of the 16-bit
free-run timer.
• When this bit is set while the compare match interrupt enable bit (IOE0: bit4) is enabled, the
output compare interrupt occurs.
• When this bit is set to "0": Clears the bit.
• Setting this bit to "1" has no effect on this bit.
• When this bit is read to a read modify write instruction, "1" is always read.
• This bit is used to enable the output compare interrupt of the compare register 1, 3, 5.
• When the compare match interrupt flag bit (IOP1: bit7) is set while "1" is written to this bit,
the output compare interrupt occurs.
• This bit is used to enable the output compare interrupt of the compare register 0, 2, 4.
• When the compare match interrupt flag bit (IOP0: bit7) is set while "1" is written to this bit,
the output compare interrupt occurs.
• This bit is used to disable the buffer function of the output compare register 1, 3, 5.
• Setting this bit to "0" enables the buffer function.
• This bit is used to disable the buffer function of the output compare register 0, 2, 4.
• Setting this bit to "0" enables the buffer function.
• This bit is used to enable the compare operation between the 16-bit free-run timer and
compare register 1, 3, 5.
• Before the compare operation is enabled, be sure to write the value to the compare register 1,
3, 5 and the timer data register (TCDTH, TCDTL).
Note:
The output compare is synchronized with the 16-bit free-run timer clock. Therefore, when the
16-bit free-run timer is stopped, the compare operation is also stopped.
• This bit is used to enable the compare operation between the 16-bit free-run timer and
compare register 0, 2, 4.
• Before the compare operation is enabled, be sure to write the value to the compare register 0,
2, 4 and the timer data register (TCDTH, TCDTL).
Note:
The output compare is synchronized with the 16-bit free-run timer clock. Therefore, when the
16-bit free-run timer is stopped, the zero detection and the compare operation are also stopped.
CHAPTER 11 MULTIFUNCTIONAL TIMER
Function
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