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■ Hold Request Cancel Level Register (HRCL)
Address
000045
H
This register is an interrupt level setting register for generating a hold request cancel request.
[bit7] MHALTI
MHALTI suppresses DMA transfer by an NMI request. This bit is set to "1" by an NMI request; writing
"0" to the bit clears it. Clear the bit at the end of the NMI routine in the same way as with an ordinary
interrupt routine.
[bit4 to bit0] LVL4 to LVL0
These bits are used to set the interrupt level for issuing a hold request cancel request to the bus master.
If an interrupt request having a higher level than that set in this register is generated, a hold request cancel
request is issued to the bus master.
The LVL4 bit is fixed at "1"; it cannot be set to "0".
7
6
5
MHALTI
–
–
R/W
CHAPTER 5 INTERRUPT CONTROLLER
4
3
2
LVL4
LVL3
LVL2
LVL1
R
R/W
R/W
R/W
← Bit No.
1
0
LVL0
HRCL
0--11111
(Initial value)
R/W
B
119
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