Fujitsu MB91260B Series Hardware Manual page 142

Example of interrupt routine
1), 3) Interrupt source clear
–
2), 4) RETI
In the above example, an interrupt of a higher priority occurs during execution of interrupt routine I.
DHREQ remains low when an interrupt of a higher level than the interrupt level set in the HRCL register
has been generated.
Note:
Pay due attention to the relationships between the interrupt levels set in the HRCL and ICR
registers.
CHAPTER 5 INTERRUPT CONTROLLER
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