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CHAPTER 3 CPU AND CONTROL UNITS
• The bit is initialized to "0" either at a reset (RST) or when a sleep-mode return source is generated.
• A read and a write are possible.
[bit5] HIZ (HIZ mode)
This bit controls the pin status during the stop mode.
0
1
• The bit is initialized to "0" at a reset (INIT).
• A read and a write are possible.
[bit4] SRST (Software ReSeT)
This bit issues a software reset (RST).
0
1
• The bit is initialized to "1" at a reset (RST).
• A read and a write are possible. Reading the bit always returns "1".
[bit3, bit2] OS1, OS0 (Oscillation Stabilization time select)
These bits are used to specify the oscillation stabilization wait time to be waited for immediately after a
reset (INIT) or a return from the stop mode.
The combination of values written to these bits selects the oscillation stabilization wait time from among
the four options listed below.
OS1
0
0
1
1
(φ represents the internal base clock period; it is twice the main oscillation.)
•
These bits are initialized to "00
• A read and a write are possible.
[bit1] (reserved bit)
• This bit is a reserved bit. Always write "1" to this bit.
[bit0] OSCD1 (Oscillation Disable mode for XIN1)
This bit controls the stopping of oscillation at main oscillation inputs (X0, X1) during the stop mode.
0
1
• This bit is initialized to "1" at a reset (INIT).
80
Maintain the pin status existing prior to transition to stop mode.
Keep pin output in high impedance state during stop mode. (Initial value)
Issue software reset.
Do not issue software reset. (Initial value)
OS0
Oscillation stabilization wait time
φ × 2
1
0
1
0
1
" at a reset (INIT) by INIT pin input.
B
Do not stop main oscillation but PLL oscillation during stop mode.
Stop main oscillation during stop mode. (Initial value)
(Initial value)
φ × 2
11
φ × 2
16
φ × 2
22
Main oscillation at 4 MHz
1.0 [µs]
1.0 [ms]
32.7 [ms]
2.0 [s]
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