CHAPTER 17 FLASH MEMORY
17.2.2
Flash Wait Register (FLWC)
The flash wait register (FLWC) controls the wait status of flash memory in CPU mode.
■ Configuration of the Flash Wait Register (FLWC)
Figure 17.2-3 shows the bit configuration of FLWC.
Address
007004
H
Functions of each bit in the flash wait register (FLWC) are described below.
[bit7, bit6] (reserved)
Reserved bits. Always set these bits to "0".
[bit5, bit4] FAC1, FAC0: These bits control the pulse width of the internal write signal.
FAC1
0
0
1
1
Note:
ATDIN and EQIN are internal write signals. Use default setting for normal use.
For MASK product, always set "00
[bit3] (reserved)
Reserved bit. Always set this bit to "0".
412
Figure 17.2-3 Bit Configuration of Flash Wait Register (FLWC)
7
6
5
–
–
FAC1
R
R/W
R/W
0
0
0
FAC0
0
1
0
1
B
4
3
2
FAC0
–
WTC2 WTC1 WTC0
R/W
R/W
R/W
0
0
0
ATDIN
0.5 clock
1 clock
1.5 clock
2 clock
".
← Bit No.
1
0
← Read/Write
R/W
R/W
← Initial value
1
1
EQIN
1 clock
(Initial value)
1.5 clock
2 clock
2.5 clock