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CHAPTER 11 MULTIFUNCTIONAL TIMER
Table 11.4-1 Timer State Control Register, Upper Byte (TCCSH) (1 / 2)
Bit Name
ECKE:
bit15
Clock select bit
IRQZF:
bit14
Zero detection
interrupt flag bit
IRQZE:
Zero detection
bit13
interrupt request
enable bit
bit12
MSI2 to MSI0:
bit11
Interrupt mask
bit10
selection bit
222
• This bit is used to select the internal clock or the external clock as a count clock of the 16-
bit free-run timer.
• Setting this bit to "0" selects the internal clock. To select a count clock frequency, you also
need to select a clock frequency select bit of the TCCSL register (CLK 3 to CLK 0: bit3 to
bit0).
• Setting this bit to "1" selects the external clock. The external clock is inputted from CKI
pins. Therefore, write "0" to the bit7 of the port direction register (DDR1) to enable the
external clock input.
Note:
The count clock is changed immediately when this bit is set. Therefore, this bit must be
changed when the output compare and the input capture are stopped.
• When the count value of the 16-bit free-run timer is "0000
• When this bit is set to "0": Clears the bit.
• Setting this bit to "1" has no effect on this bit.
• When this bit is read to a read modify write instruction, "1" is always read.
Note:
In the up count mode (the lower of the timer state control register (TCCSL), MODE: bit5 =
0), this bit is set to "1" when the interrupt defined in the interrupt mask select bit (the upper
of the timer state control register (TCCSH), MSI 2 to MSI 0: bit12 to bit10 is the value other
than "000
") occurs. When no interrupt occurs, this bit is not set to "1".
B
In the up count mode (MODE: bit5 = 1), this bit is set every time the zero detection occurs
regardless of the value for the MSI 2 to MSI 0: bit12 to bit10.
When the timer count clock is the machine cycle (φ)
The software clear (TCCSL: bit4 SCLR = 1) cannot be set this bit.
When the timer count clock is the machine cycle (φ) division
The software clear (TCCSL: bit4 SCLR = 1) can set this bit.
When this bit and the interrupt flag bit (IRQZF: bit14) are set to "1", an interrupt request to the
CPU can be generated.
• In the up count mode (MODE = 0), these bits are used to set the number of masking of the
compare clear interrupt. In up/down count mode (MODE = 1), they are used to set the
number of masking for the zero detection interrupt.
• Setting these bits to "0" do not mask the interrupt cause.
Note:
When the interrupt cause has been masked twice, and then the third interrupt is processed,
these bits must be set to "010
The read value is masked count value.
Function
".
B
", this bit is set to "1".
H
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