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Note:
For transition to standby mode, select the synchronous standby mode (using the SYNCS bit (bit8) in
the TBCR (timebase counter control register)) and be sure to use the following sequence:
/* Writing STCR */
ldi
ldi
stb
/* Writing STBR */
ldi
ldi
stb
ldi
stb
/* Clearing the time base counter in here */
ldub
/* Starting synchronous standby transition */
ldub
nop
nop
nop
nop
nop
Each bit in the standby control register (STCR) functions as follows:
[bit7] STOP (STOP mode)
This bit selects whether to cause a transition to the stop mode. If "1" is written to both of this bit and the
SLEEP bit (bit6), this bit overrides the other, causing a transition to the stop mode.
0
1
• The bit is initialized to "0" either at a reset (RST) or when a stop-mode return source is generated.
• A read and a write are possible.
[bit6] SLEEP (SLEEP mode)
This bit selects whether to cause a transition to the sleep mode. If "1" is written to both of this bit and the
STOP bit (bit7), the STOP bit (bit7) overrides this bit, causing a transition to the stop mode.
0
1
#_STCR, R0
#Val_of_Stby, rl
rl,@r0
#_CTBR, r2
#0xA5, rl
rl,@r2
#0xA5, rl
rl,@r2
@r0, rl
@r0, rl
Do not enter stop mode. (Initial value)
Enter stop mode.
Do not enter sleep mode. (Initial value)
Enter sleep mode.
CHAPTER 3 CPU AND CONTROL UNITS
; STCR register (0x0481)
; Val_of_Stby is the write data to STCR.
; Writing to STCR
; CTBR register (0x0483)
; Clear command (1)
; Writing A5 to CTBR
; Clear command (2)
; Writing A5 to CTBR
; Reading STCR
; Reading dummy STCR
; NOP × 5 for timing adjustment
79
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