Fujitsu MB91260B Series Hardware Manual page 404

■ Step/block Transfer Two-cycle Transfer
For step or block transfer (only transfer the specified number of blocks for each transfer request), the
transfer source and destination addresses can be specified as 20-bit addresses for ch0 to ch3, and as 24-bit
addresses for ch4.
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Step transfer
The step transfer sequence is used if the block size is set to "1".
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Step transfer characteristics
• Each time a transfer request is received, one transfer is performed, and then the transfer request is
cleared and transfer halts. (The DMA transfer request is removed from the bus controller.)
• If another transfer request is received during a transfer, the request is ignored.
• If a transfer request for a channel with a higher priority is received during a transfer, the DMAC changes
channel and starts the next transfer after the previous transfer completes. For step transfer, priority is
only meaningful for the case when transfer requests are generated simultaneously.
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Block transfer
The block transfer sequence is used if the block size is set to a value other than "1".
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Block transfer characteristics
Except for the fact that each transfer consists of multiple transfer cycles (specified by the number of
blocks), the operation is the same as for step transfer.
Figure 16.5-2 Block Transferring Example at Peripheral Transfer Request, Block Number = 2,
Peripheral transfer request
Bus operation
Block number
Transferring number
Transfer end (internal)
Transferring Number = 2
CPU SA DA
2
2
SA DA CPU
1 0
CHAPTER 16 DMAC (DMA Controller)
SA DA SA
2 1
1
DA
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