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B3
B2
B1
B0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
...
...
...
...
1
1
1
1
(φ represents the internal base clock period.)
• These bits are initialized to "0000
• A read and a write are possible.
[bit11 to bit8] P3, P2, P1, P0 (clkP divide select 3 to 0)
These bits are used to set the peripheral clock (CLKP) frequency divide ratio.
The clock frequency divide ratio set by these bits applies to the clock signal (CLKP) for peripheral circuits
and peripheral buses.
The combination of values written to these bits selects the divide ratio (clock frequency) for the peripheral
circuit/peripheral bus clock signal relative to the base clock signal, from among the 16 types listed below.
Do not set the bits to a divide ratio which results in a frequency higher than the maximum operating
frequency.
P3
P2
P1
P0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
...
...
...
...
1
1
1
1
(φ represents the system base clock period.)
• These bits are initialized to "0011
•
A read and a write are possible.
Clock divide ratio
φ
φ × 2 (Divide by 2)
φ × 3 (Divide by 3)
φ × 4 (Divide by 4)
φ × 5 (Divide by 5)
φ × 6 (Divide by 6)
φ × 7 (Divide by 7)
φ × 8 (Divide by 8)
...
φ × 16 (Divide by 16)
" at a reset (INIT).
B
Clock divide ratio
φ
φ × 2 (Divide by 2)
φ × 3 (Divide by 3)
φ × 4 (Divide by 4)
φ × 5 (Divide by 5)
φ × 6 (Divide by 6)
φ × 7 (Divide by 7)
φ × 8 (Divide by 8)
...
φ × 16 (Divide by 16)
" at a reset (INIT).
B
CHAPTER 3 CPU AND CONTROL UNITS
Clock frequency: Oscillation frequency
of 4 MHz and main PLL multiplier of 8×
32 MHz (Initial value)
16 MHz
10.7 MHz
8 MHz
6.4 MHz
5.33 MHz
4.57 MHz
4 MHz
...
2 MHz
Clock frequency: Oscillation frequency of
4 MHz and main PLL multiplier of 8×
32 MHz
16 MHz
10.7 MHz
8 MHz (Initial value)
6.4 MHz
5.33 MHz
4.57 MHz
4 MHz
...
2 MHz
87
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