Fujitsu MB91260B Series Hardware Manual page 98

[bit8] SYNCS (SYNChronous Standby enable)
This bit serves as the synchronous standby operation enable bit.
To use the standby mode (sleep mode or stop mode), be sure to set the bit to "1".
0
1
• The bit is initialized to "0" at a reset (INIT).
• A read and a write are possible.
■ CTBR: Timebase Counter Clear Register
Address: 000483
Initial value (INIT)
Initial value (RST)
This register initializes the timebase counter.
When "A5
cleared to "0" immediately after the "5A
write and "5A
must be written again before "5A
Note, however, that the FF is cleared automatically when the CPU is not operating such as in the stop or
sleep mode or during DMA transfer. If such a condition develops, therefore, a watchdog reset is deferred
automatically. For details, see the section "3.11.7 Peripheral Circuits in the Clock Control Unit".
The value read from this register is indeterminate.
Note:
Clearing the timebase counter using this register temporarily changes the oscillation stabilization wait
time, watchdog timer interval, and timebase timer interval.
■ CLKR: Clock Source Control Register
Address: 00000484
Initial value (INIT)
Initial value (RST)
This register selects the clock source as the internal base clock and controls the main PLL.
Use this register to select the clock source, enable or disable main PLL operation, and select the PLL
multiplier.
[bit15] (reserved bit)
This bit is a reserved bit. Always write "0" to this bit.
Normal standby operation (Initial value)
Synchronous standby operation
Bit 7
D7
H
W
×
×
" and "5A " are written to this register in succession, all the bits in the timebase counter are
H H
" write. If any data other than "5A
H
" is written in order to clear the timebase counter.
H
Bit 15
PLL1S2 PLL1S1 PLL1S0
–
H
R/W
0
×
CHAPTER 3 CPU AND CONTROL UNITS
6 5 4
D6 D5 D4
W W W
× × ×
× × ×
" write. There is no restriction on the interval between "A5
H
" is written following the "A5
H
14 13 12
R/W R/W R/W
0 0 0
× × ×
3 2 1
D3 D2 D1
W W W
× × ×
× × ×
" write, however, "A5
H
11 10 9
PLL1EN CLKS1 CLKS0
–
R/W R/W R/W
0 0 0
× × ×
0
D0
W
×
×
"
H
"
H
8
R/W
0
×
83