Fujitsu MB91260B Series Hardware Manual page 277

CHAPTER 11 MULTIFUNCTIONAL TIMER
Count value
FFFF
H
BFFF
H
7FFF
H
3FFF
H
0000
H
Start timer operation
Reset
Compare clear
buffer register
TCCSL: MODE
■ Compare Clear Buffer
The compare-clear register (CPCLRH/CPCLRL) has a buffer feature that can be enabled or disabled. If the
buffer feature is enabled (TCCSL register's BFE: bit7 = 1), data written to the compare-clear buffer register
(CPCLRBH/CPCLRBL) is sent to the CPCLRH/CPCLRL register when a value of 0 is detected in the 16-
bit free-run timer. When the buffer feature is disabled (TCCSL bits' BFE: bit7 = 0), the CPCLRBH/
CPCLRBL register becomes permeable, and data can be written directly to the CPCLRH/CPCLRL register.
Figure 11.6-3 Operation in Up Count Mode when Compare Clear Buffer Is Disabled
Count value
FFFF
H
BFFF
H
7FFF
H
3FFF
H
0000
H
Start timer operation
Reset
Compare clear
buffer register
Compare clear
register
Figure 11.6-4 Operation in Up Count Mode when Compare Clear Buffer Is Enabled
Count value
FFFF
H
BFFF
H
7FFF
H
3FFF
H
0000
H
Start timer operation
Reset
Compare clear
buffer register
Compare clear
register
262
Figure 11.6-2 Change Timer Mode during Timer Operation
Change to up-count mode
Change to up/down count mode
(TCCSL Register's BFE: Bit7 = 0)
Compare clear match
Zero detection
BFFF
H
BFFF
H
(TCCSL Register's BFE: Bit7 = 1)
Compare clear match
Zero detection
7FFF
BFFF
H
BFFF
H
BFFF
H
7FFF
H
7FFF
H
H
7FFF
H
FFFF
H
FFFF
H
FFFF
H
FFFF
H
Timer
Timer
Timer