Fujitsu MB91260B Series Hardware Manual page 230

■ 16-bit Input Capture Registers
Input capture data register (Upper)
IPCPH0 to IPCPH3
Address :
0000AC
H
0000AE
Read →
H
0000B0
Initial value →
H
0000B2
H
Input capture data register (Lower)
IPCPL0 to IPCPL3
Read →
Initial value →
Input capture state control register (ch2,3) (Upper)
ICSH23
Address: 0000B6
H
Read →
Initial value →
Input capture state control register (ch2,3) (Lower)
ICSL23
Address: 0000B7
Read/Write →
Initial value →
PPG output control / Input capture state control register (ch0,1) (Upper)
PICSH01
Address: 0000B4
H
Write →
Initial value →
Input capture state control register (ch0,1) (Lower)
PICSL01
Address: 0000B5
Read/Write →
Initial value →
Bit15 Bit14
CP15 CP14
R R
(X) (X)
Bit7 Bit6
CP07 CP06
R R
(X) (X)
Bit15 Bit14
- -
- -
(X) (X)
Bit7 Bit6
H
ICP3 ICP2
R/W R/W
(0) (0)
Bit15 Bit14
PGEN5 PGEN4
W W
(0) (0)
Bit7 Bit6
H
ICP1 ICP0
R/W R/W
(0) (0)
CHAPTER 11 MULTIFUNCTIONAL TIMER
Bit13 Bit12 Bit11
CP13 CP12 CP11
R R R
(X) (X) (X)
Bit5 Bit4 Bit3
CP05 CP04 CP03
R R R
(X) (X) (X)
Bit13 Bit12 Bit11
- - -
- - -
(X) (X) (X)
Bit5 Bit4 Bit3
ICE3 ICE2 EG31
R/W
R/W R/W
(0)
(0) (0)
Bit13 Bit12 Bit11
PGEN3 PGEN2 PGEN1
W
W W
(0)
(0) (0)
Bit5 Bit4 Bit3
ICE1 ICE0 EG11
R/W R/W R/W
(0) (0) (0)
Bit10 Bit9 Bit8
CP10 CP09 CP08
R R R
(X) (X) (X)
Bit2 Bit1 Bit0
CP02 CP01 CP00
R R R
(X) (X) (X)
Bit10 Bit9 Bit8
- IEI3 IEI2
- R R
(X) (0) (0)
Bit2 Bit1 Bit0
EG30 EG21 EG20
R/W R/W R/W
(0) (0) (0)
Bit10 Bit9 Bit8
- -
PGEN0
W - -
(0) (X) (X)
Bit2 Bit1 Bit0
EG10 EG01 EG00
R/W R/W R/W
(0) (0) (0)
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