Table 5.3-1 Interrupt Sources, Interrupt Numbers, and Interrupt Levels (1 / 3)
Interrupt Source
Reset
Mode vector
System-reserved
System-reserved
System-reserved
System-reserved
System-reserved
Coprocessor absence trap
Coprocessor error trap
INTE instruction
System-reserved
System-reserved
Step trace trap
NMI request (tool)
Undefined instruction exception
NMI request
External interrupt 0
External interrupt 1
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
External interrupt 7
Reload timer 0
Reload timer 1
Reload timer 2
UART0 (Reception complete)
Interrupt No.
Hexa-
Decimal
decimal
0
00
1
01
2
02
3
03
4
04
5
05
6
06
7
07
8
08
9
09
10
0A
11
0B
12
0C
13
0D
14
0E
15
0F
16
10
17
11
18
12
19
13
20
14
21
15
22
16
23
17
24
18
25
19
26
1A
27
1B
CHAPTER 5 INTERRUPT CONTROLLER
Interrupt
Offset
Level
3FC
–
H
3F8
–
H
3F4
–
H
3F0
–
H
3EC
–
H
3E8
–
H
3E4
–
H
3E0
–
H
3DC
–
H
3D8
–
H
3D4
–
H
3D0
–
H
3CC
–
H
3C8
–
H
3C4
–
H
15(F
) Fixed
3C0
H
H
3BC
ICR00
H
3B8
ICR01
H
3B4
ICR02
H
3B0
ICR03
H
3AC
ICR04
H
3A8
ICR05
H
3A4
ICR06
H
3A0
ICR07
H
39C
ICR08
H
398
ICR09
H
394
ICR10
H
390
ICR11
H
TBR Default
RN
Address
000FFFFC
–
H
000FFFF8
–
H
000FFFF4
–
H
000FFFF0
–
H
000FFFEC
–
H
000FFFE8
–
H
000FFFE4
–
H
000FFFE0
–
H
000FFFDC
–
H
000FFFD8
–
H
000FFFD4
–
H
000FFFD0
–
H
000FFFCC
–
H
000FFFC8
–
H
000FFFC4
–
H
000FFFC0
–
H
000FFFBC
6
H
000FFFB8
7
H
000FFFB4
–
H
000FFFB0
–
H
000FFFAC
–
H
000FFFA8
–
H
000FFFA4
–
H
000FFFA0
–
H
000FFF9C
8
H
000FFF98
9
H
000FFF94
10
H
000FFF90
0
H
121